1. Technical Field
The present disclosure relates to a switching regulator to supply a highly precise voltage to a load circuit (e.g., a CPU, etc.), and an electronic device employing the switching regulator.
2. Description of the Related Art
At present, varieties of different applications are typically installed in mobile phones. The applications themselves tend to consume battery power at very high rates, and as a result, a power supply circuit whose external components are compact while at the same time able to handle large currents and low output voltages is needed. In addition, improvements in discharge characteristics of the lithium ion battery used as a primary power supply on the mobile phone side have widened the voltage range available for input to the power supply circuit. Further, it is now common to optimize the operating speed and power consumption of a load circuit (e.g., CPU) connected to an output terminal of the power supply circuit by changing a set voltage of the power supply circuit depending on the operation state of the CPU. Therefore, power supply circuit that can keep the output voltage constant even when an input voltage, an output voltage, or an output current is changed is required.
For example, a first related art proposes a power supply device to avoid deterioration in output voltage characteristics even when an output load current fluctuates. A second related art proposes a DC-DC converter to stabilize a switching frequency. A third related art proposes a switching regulator to be made more compact.
FIG. 6 is a circuit diagram illustrating a conventional switching regulator 1P as the first related art. The switching regulator 1P is one example of a ripple detection-type switching regulator having a switching element whose length of ON-period is fixed. FIG. 7 is a circuit diagram illustrating a switching-time control circuit 3P in the switching regulator 1P shown in FIG. 6. FIG. 8 is a timing chart illustrating operation of the switching regulator 1P show in FIG. 6.
In FIG. 6, the switching regulator 1P includes a switching-element control circuit 2, a comparator 6, the switching-time control circuit 3P, an input terminal TI to which an input voltage VIN is input, an output terminal LX, a switching element SW1 connected between the input terminal TI and the output terminal LX, a switching element SW2 connected between the output terminal LX and a ground voltage, a dividing circuit 7 including a dividing resistor 8 having resistance Rf1 and a dividing resistor 9 having resistance Rf21, and a feedback terminal TF. Further, the switching-element control circuit 2 includes a RS flip-flop circuit 22 and a control-signal generator circuit 23.
Further, in FIG. 7, the switching-time control circuit 3P includes a reference current source 51 that has one terminal connected to the input terminal TI and outputs a predetermined reference current Ic, a capacitor 52 connected between the reference current source 51 and the ground voltage, having a capacitance Cc, a switching element SW5 connected in parallel to the capacitor 52, a voltage source 54 to output a predetermined reference voltage VR, and a comparator 53.
In FIG. 6, the output voltage output from the output terminal LX is output to a load circuit 10 (e.g., CPU) via a high-frequency removal and smoothing low-pass filter 15 constituted by an inductor 12 having inductance L and an output capacitor 14 having capacitance Cout. Herein, a resistor 13 that has resistance Resr is a serial equivalent parasitic resistor of the output capacitor 14. The output voltage VOUT from the low-pass filter 15 is input to the switching regulator 1P via the feedback terminal TF and is divided by the dividing circuit 7.
Then, the feedback voltage VF after dividing is output to au inserting input terminal (−) of the comparator 6. The comparator 6 compares the feedback voltage VF with a predetermined reference voltage VREF input from a voltage source 11 to the non-inverting input terminal (+) of the comparator 6. The comparator 6 outputs a low-level switching-time control signal CMPO-P to a set terminal S of the RS flip-flop circuit 22 when the feedback voltage VF is greater than the reference voltage VREF, and outputs a high-level switching-time control signal CMPO-P to the set terminal S of the RS flip-flop circuit 22 when the feedback voltage VF is smaller than the reference voltage VREF. Herein, the high-level switching-time control signal CMPO-P, serving as the second switching-time control signal, indicates a finish timing of an ON-period of the switching element SW2.
With reference to FIG. 7, the switching-time control circuit 3P generates a switching-time control signal TON-P indicating a finish timing of an ON-period of the switching element SW1 for output to a reset terminal R of the RS flip-flop circuit 22. In addition, an output signal PSET from the RS flip-flop circuit 22 is output to the control-signal generator circuit 23. The control-signal generator circuit 23 generates a switching-element control signal PDRV to control switching of the switching element SW1 and a switching-element control signal NDRV to control switching of the switching element SW2 so that the ON-period of the switching element SW1 is finished when the output signal PSET falls, and the ON-period of the switching element SW2 is finished when the output signal PSET rises, and the switching elements SW1 and SW2 are turned on and off complementarily. In addition, the control-signal generator circuit 23 generates an output signal TCHGB1 in synchrony with the switching-element control signal PDRV and outputs the output signal TCHGB1 to the switching-time control circuit 3P. It is to be noted that the switching element SW1 is turned on in response to a low-level switching-element control signal PDRV and is turned off in response to a high-level switching-element control signal PDRV. In addition, the switching element SW2 is turned on in response to a high-level switching-element control signal NDRV and is turned off in response to a low-level switching-element control signal NDRV. The switching elements SW1 and SW2 are controlled so that the switching element SW2 is turned on when the switching element SW1 is turned on and the switching element SW1 is turned on when the switching element SW2 is turned off.
In FIG. 7, the voltage source 54 generates a predetermined reference voltage VR for output to an inverting input terminal (−) of the comparator 53. A voltage VC at a junction node between the reference current source 51 and the capacitor 52 is output to a non-inverting input terminal (+) of the comparator 53. The output signal TCHGB1 is output to a gate of the switching element SW5. Therefore, the switching element SW5 is turned off in response to the output signal TCHGB1 while the switching element SW1 is on. Conversely, the switching element SW5 is turned on while the switching element SW1 is off state. In addition, the comparator 53 compares the voltage VC with the reference voltage VR. The comparator 53 outputs a high-level switching-time control signal TON-P when the voltage VC is greater than the reference voltage VR, and outputs a low-level switching-time control signal TON-P when the voltage VC is smaller than the reference voltage VR.
In FIG. 6, when the feedback voltage VF becomes smaller than the reference voltage VREF, the voltage level of the switching-time control signal CMPO-P output from the comparator 6 becomes high. In response to this operation, the RS flip-flop circuit 22 is set, and the voltage level of the output signal PSET becomes high. Then, the control-signal generator circuit 23 generates the switching-element control signals PDRV and NDRV so that the switching element SW1 is switched on and the switching element SW2 is switched off. In response to this operation, while the switching element SW1 is turned on, the switching element SW2 is turned off, and energy is charged in the inductor 12 by a difference voltage between the input voltage VIN and the output voltage VOUT. Accordingly, an inductor current in the inductor 12 is increased, and the output voltage VOUT is increased by the output capacitor 14 and its serial equivalent parasitic 13.
Subsequently, when the ON-period of the switching element SW1 has elapsed at a predetermined time, the voltage level of the switching-time control signal TON-P changes from low to high. In response to this, the RS flip-flop circuit 22 is reset, and the voltage level of the output signal PSET from the RS flip-flop circuit 22 becomes low. The control-signal generator circuit 23 generates the switching-element control signals PDRV and the NDRV so that the switching element SW1 is turned off and the switching element SW2 is turned on. In response to this, while the switching element SW1 is turned off, the switching element SW2 is turned on, and the energy in the inductor 12 is released by the difference in voltage between the ground voltage and the output voltage VOUT. Accordingly, as the inductor current in the inductor 12 is decreased, the output voltage VOUT is decreased by the capacitor 14 and its serial equivalent parasitic resistor 13.
Herein, a length of the ON-period “ton1” of the switching element SW1 is determined as follows. In FIG. 7, while the switching element SW1 is off state in response to the low-level switching-element control signal PDRV, the switching element SW5 is turned off in response to the output signal TCHGB1 in synchrony with the switching-element control signal PDRV, and the capacitor 52 is charged at the reference current Ic. The comparator 53 compares the voltage VC across the charged capacitor 52 with the reference voltage VR. The comparator 53 outputs the high-level switching-time control signal TON-P when the voltage VC is greater than the reference voltage VR, and outputs the low-level switching-time control signal TON-P when the voltage VC is smaller than the reference voltage VR. In addition, in a period during which the switching element SW1 is off and the switching element SW2 is on, the switching element SW5 is turned on in response to the high-level output signal TCHGB1 from the control-signal generator circuit 23, and the charge in the capacitor 52 is fully discharged.
At this, a length of n ON-period “ton1” of the switching element SW1 is obtained as follows,ton1=Cc×VR/Ic  (1)
As described above, in the switching regulator 1P shown in FIG. 6, the length of the ON-period ton1 of the switching element SW1 is determined in response to the switching-time control signal TON-P, and a length of an OFF-period “toff1” of the switching element SW1 is determined by the switching-time control signal CMPO-P from the comparator 6 as a comparison result between the feedback voltage VF and the reference voltage VREF. As described above, by repeating on and off of the switching elements SW1 and SW2, the switching regulator 1P controls the output voltage so that a lime-averaged voltage VOUTa of the output voltage VOUT is set to be constant.
However, in the circuit configuration shown in FIG. 6, since the length of the ON-period ton1 is a fixed value calculated by formula 1, the amount of increase Δφon in magnetic flux of the inductor 12 when the switching element SW1 is on and the amount of decrease Δφoff in the magnetic flux of the inductor 12 when the switching element SW1 is off are calculated by the following formulas, using the input voltage YIN, the output voltage VOUT, an on-resistance Ron of the respective switching elements SW1 and SW2, and an inductor current IL of the inductor 12.Δφon=(VIN−IL×Ron−VOUT)×ton1  (2)Δφoff=(VOUT+IL×Ron)×toff1  (3)
In addition, as the amount of the increase Δφon in the magnetic flux is equal to the amount of decrease Δφoff therein (Δφon=Δφoff), a switching cycle tsw (tsw=ton1+toff1) can be calculated as follows:
                    tsw        =                              VIN            ×            to            ⁢                                                  ⁢            n            ⁢                                                  ⁢            1                                VOUT            +                          IL              ×              Ron                                                          (        4        )            
Accordingly, a switching frequency fsw holds:
                    fsw        =                              1            tsw                    =                                    VOUT              +                              IL                ×                Ro                ⁢                                                                  ⁢                n                                                    VIN              +                              to                ⁢                                                                  ⁢                n                ⁢                                                                  ⁢                1                                                                        (        5        )            
As is clear from formula 5, as the input voltage VIN, the output voltage VOUT, the inductor current IL (output current Iout to the load circuit 10) fluctuate, the fluctuation in the switching frequency fsw becomes greater. In addition, the time-averaged voltage VOUTa of the output voltage VOUT cannot be kept constant, which degrades the accuracy of the output voltage.
For example, as illustrated in FIG. 7, representing a first switching cycle tsw1 as a cycle when the output current IOUT is a first current I1, and a second switching cycle tsw2 as a cycle when the output current IOUT is increased to a second current I2 (I1<I2), the second switching cycle tsw2 that is longer than the first switching cycle tsw1 (tsw1>tsw2) because the first current I1 is smaller than the second current I2. In other words, a switching frequency fsw1 when the output current IOUT is the first current I1 is greater than a switching frequency fsw2 when the output current IOUT is the second current I2. As is clear from FIG. 7, when the output current IOUT is increased from the first current I1 to the second current I2, the time-averaged voltage VOUTa of the output voltage VOUT (corresponding to the feedback voltage VF) is decreased. Similarly, as is clear from formulas 4 and 5, when the input voltage VIN or the output current IOUT (corresponding to the inductor current IL) is changed, the switching frequency fsw and the output voltage VOUT are changed.
JP-2010-200450-A proposes a configuration in which a power supply device alleviates the influence from an input voltage, an output voltage, and the output current, and improves the accuracy of the switching frequency. In this example, the power supply device controls respective switching elements based on the input voltage, the output voltage, and the output current to improve characteristics of the output voltage.
FIG. 9 is a circuit diagram illustrating this conventional power supply device 1000. FIG. 10 is a circuit diagram illustrating a TON generator 102 in the power supply device 1000 shown in FIG. 9. In FIG. 9, the power supply device 1000 includes a current detection circuit 108 to feedback an output current Io. In FIG. 10, the TON generator 102 includes a resistor network to feedback an input voltage VIN, operation amplifiers 121 and 127, a resistor network to feedback to an output voltage Vo, and an adder 128 to add a voltage corresponding to the output voltage Vo and a voltage Vs corresponding to the output current Io. With this configuration, the chip size and current consumption may be increased. Therefore, the power supply 1000 is not suitable for the power supply circuit used for the portable device that is required to be compact and energy-efficient (low current consumption.)
In addition, a switching frequency fsw in the power supply circuit 1000 is obtained as below, using an input voltage VIN and an inductor current ILX flowing through a transistor 151, with reference to FIGS. 9 and 10.fsw=VIN/(VIN−ILX×k)  (6)
The constant number k in the formula is determined by the element values of the respective elements constituting the current detection circuit 108 and the TON generator 102. That is, the switching frequency fsw is determined by the values of the input voltage VIN and the inductor current ILX, and accordingly, the switching frequency cannot be completely eliminated from dependency on the input voltage VIN and the output voltage Vo. In particular, when an external load Ro is CPU, a load current (output current) precipitously fluctuates continuously. Therefore, the switching frequency fluctuates every time the load current fluctuates, thus generating a switching noise in wide band, which have serious impact on peripheral equipments.